SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D.C 20549 FORM 10-K COMMISSION FILE NUMBER: 0-18032 /X/ Annual report pursuant to Section 13 or 15(d) of the Securities Exchange Act of 1934 for the fiscal year ended April 3, 1999 or / / Transition report pursuant to Section 13 or 15(d) of the Securities Exchange Act of 1934 For the transition period from to ------- ------- LATTICE SEMICONDUCTOR CORPORATION (Exact name of Registrant as specified in its Charter) DELAWARE 93-0835214 (State of Incorporation) (I.R.S Employer Identification No.) 5555 NE MOORE COURT, HILLSBORO, OREGON 97124-6421 (Address of principal executive offices) (Zip Code) Registrant's telephone number, including area code: (503) 268-8000 SECURITIES REGISTERED PURSUANT TO SECTION 12(b) OF THE ACT: NONE SECURITIES REGISTERED PURSUANT TO SECTION 12(g) OF THE ACT: Title of Class Name of Exchange Common Stock, $.01 par value NASDAQ Preferred Share Purchase Rights None Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes X No --- --- Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. Yes X No --- --- As of June 17, 1999, the aggregate market value of the shares of voting stock of the Registrant held by non-affiliates was approximately $821 million. Shares of Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock have been excluded in that such persons may be deemed affiliates. This determination of affiliate status is not necessarily a conclusive determination for other purposes. As of June 17, 1999, 23,711,652 shares of the Registrant's common stock were outstanding. DOCUMENTS INCORPORATED BY REFERENCE 1. Portions of the Annual Report to Stockholders for the fiscal year ended April 3, 1999 are incorporated by reference in Part II hereof. 2. Portions of the definitive proxy statement of the Registrant to be filed pursuant to Regulation 14A for the 1999 Annual Meeting of Stockholders to be held on August 9, 1999 are incorporated by reference in Part III hereof.
LATTICE SEMICONDUCTOR CORPORATION FORM 10-K ANNUAL REPORT TABLE OF CONTENTS <TABLE> <CAPTION> Item of Form 10-K Page - ----------------- ---- <S> <C> PART I Item 1 - Business.............................................................................. 2 Item 2 - Properties............................................................................15 Item 3 - Legal Proceedings.....................................................................16 Item 4 - Submission of Matters to a Vote of Security Holders...................................16 Item 4(a) - Executive Officers of the Registrant..................................................17 PART II Item 5 - Market for the Registrant's Common Stock and Related Stockholder Matters..............19 Item 6 - Selected Financial Data...............................................................19 Item 7 - Management's Discussion and Analysis of Financial Condition and Results of Operations........................................................................20 Item 7(a) - Quantitative and Qualitative Disclosures about Market Risk............................20 Item 8 - Financial Statements and Supplementary Data...........................................20 Item 9 - Changes in and Disagreements with Accountants on Accounting and Financial Disclosure...........................................................................21 PART III Item 10 - Directors and Executive Officers of the Registrant....................................22 Item 11 - Executive Compensation................................................................22 Item 12 - Security Ownership of Certain Beneficial Owners and Management........................22 Item 13 - Certain Relationships and Related Transactions........................................22 PART IV Item 14 - Exhibits, Financial Statement Schedules and Reports on Form 8-K.......................23 Signatures..............................................................................................27 Financial Statement Schedules...........................................................................S-1 </TABLE> 1
ITEM 1. BUSINESS This Report contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended. Actual results could differ materially from those projected in the forward-looking statements as a result of the factors set forth in "Factors Affecting Future Results" and elsewhere in this Report. GENERAL Lattice Semiconductor Corporation (the "Company") designs, develops and markets high performance programmable logic devices ("PLDs") and related development system software. The Company is the inventor and world's leading supplier of in-system programmable ("ISP-TM-") PLDs. The Company introduced ISP devices to the industry in 1992. PLDs are standard semiconductor components that can be configured by the end customer as specific logic functions, enabling shorter design cycle times and reduced development costs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to original equipment manufacturers ("OEMs") of communication, computing, industrial and military systems. Lattice was founded in 1983 and is based in Hillsboro, Oregon. In June 1999, the Company acquired Vantis Corporation from Advanced Micro Devices ("AMD") for approximately $500 million in cash. Vantis will be integrated into the operations of the Company and remain a wholly-owned subsidiary of the Company. The business of Vantis is substantially similar to that of the Company including markets, products, customers, work force and revenues, which are not included in the descriptions, Technology, Products, Product Development, Operations, Marketing, Sales, Customers, Backlog, Licenses and Agreements and Year 2000 Compliance contained herein. Prior to the acquisition, Vantis relied upon its parent company, AMD, for most manufacturing activities as well as financial and administrative services. As a part of the acquisition agreement between AMD and the Company, AMD has agreed to continue to perform many of these services for defined periods or at the Company's option, shorter periods. The transaction is being accounted for using the purchase method in the Company's consolidated financial statements beginning in the period ended July 3, 1999. As part of the acquisition agreements, AMD and the Company have agreed to sign an election under the Internal Revenue Code which will enable the Company to take a tax deduction for the purchase price amortized over periods up to 15 years. The primary benefits expected to result from this acquisition are accelerated development of new products and new technologies, and the ability to reach and service a greater number of customers. PLD MARKET BACKGROUND Three principal types of digital integrated circuits are used in most electronic systems: microprocessors, memory and logic. Microprocessors are used for control and computing tasks, memory is used to store programming instructions and data, and logic is employed to manage the interchange and manipulation of digital signals within a system. Logic contains interconnected groupings of simple logical "AND" and logical "OR" functions, commonly described as "gates". Typically, complex combinations of individual gates are required to implement the specialized logic functions required for systems applications. While system designers use a relatively small number of standard architectures to meet their microprocessor and memory needs, they require a wide variety of logic circuits in order to achieve end product differentiation. Logic circuits are found in a wide range of today's digital electronic equipment including communication, computing, industrial and military systems. According to WSTS, a semiconductor industry association, logic 2
accounted for approximately 28% of the estimated $109 billion worldwide digital integrated circuit market in 1998. The logic market encompasses, among other segments, standard logic, custom-designed application specific integrated circuits ("ASICs", which include conventional gate-arrays, standard cells and full custom logic circuits), and PLDs. Manufacturers of electronic equipment are increasingly challenged to bring differentiated products to market quickly. These competitive pressures often preclude the use of custom-designed ASICs, which generally entail significant design risks and time delay. Standard logic products, an alternative to custom-designed ASICs, limit a manufacturer's flexibility to adequately customize an end system. Programmable logic addresses this inherent dilemma. PLDs are standard products, purchased by systems manufacturers in a "blank" state, that can be custom configured into a virtually unlimited number of specific logic functions by programming the device with electrical signals. PLDs give system designers the ability to quickly create their own custom logic functions to provide product differentiation without sacrificing rapid time to market. Certain PLD products, including the Company's, are reprogrammable, meaning that the logic configuration can be modified, if needed, after the initial programming. In-system programmable PLDs, first pioneered by the Company, extend the flexibility of standard reprogrammable PLDs by allowing the system designer to configure and reconfigure the logic functions of the PLD with standard 5-volt or 3.3-volt power supplies without removing the PLD from the system board. The PLD market has two primary segments: low-density PLDs (less than 1,000 logic gates) and high-density PLDs (greater than 1,000 logic gates). High-density PLD devices include devices based on both the complex PLD ("CPLD") and field programmable gate array ("FPGA") architectures. Products based on these alternative high-density PLD architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture. CPLDs are characterized by a regular building block structure of wide-input logic cells, termed macrocells, and use of a centralized logic interconnect scheme. CPLDs are optimal for control logic applications, such as state machines, bus arbitration, encoders, decoders and sequencers. FPGAs are characterized by a narrow-input logic cell and use a distributed interconnect scheme. FPGAs are optimal for register intensive and data path logic applications such as interface logic and arithmetic functions. The Company believes that a substantial portion of high-density PLD customers utilize both CPLD and FPGA architectures within a single system design, partitioning logic functions across multiple devices to optimize overall system performance and cost. TECHNOLOGY The Company believes that electrically erasable CMOS ("E2CMOS-Registered Trademark-") is the preferred process technology for PLD products due to its inherent performance, reprogrammability and testability benefits. E2CMOS technology, through its fundamental ability to be programmed and erased electronically, serves as the foundation for the Company's ISP products. IN-SYSTEM PROGRAMMABLE (ISP) PRODUCTS AND TECHNOLOGY The Company pioneered the development of ISP products which utilize 5-volt or 3.3-volt programming signals and, as a result, can be configured and reconfigured by a system designer without being removed from the printed circuit board. Standard E2CMOS programmable logic devices require a 12-volt programming signal and therefore must be removed from the printed circuit board and programmed using specialized hardware. ISP devices offer 3
enhanced flexibility versus standard PLDs and provide significant customer benefits. ISP devices can allow customers to reduce design cycle times, accelerate time to market, reduce prototyping costs, reduce manufacturing costs and lower inventory requirements. ISP devices can also provide customers the opportunity to perform simplified and cost-effective field reconfiguration through a data file transferred by computer disk or serial data signal. PRODUCTS ISP PRODUCTS SILICON. The Company first entered the ISP market in fiscal 1993 and currently offers seven distinct families of ISP products, each consisting of multiple devices. The Company is currently shipping over 300 performance, package and temperature range combinations of ISP products. ispLSI-Registered Trademark- 1000/E: The Company's original ISP family utilizes an innovative, proprietary CPLD architecture incorporating familiar GAL-Registered Trademark- ("Generic Array Logic") based logic building blocks. This family provides performance of up to 125 MHz (7.5 nanosecond propagation delay), densities of 2,000 to 8,000 gates and is available in 44- to 128-pin standard surface mount packages. ispLSI 2000E/VE: Introduced in fiscal 1999, the SuperFAST-TM- 5 volt ispLSI 2000E and 3.3 volt ispLSI 2000VE families utilize an architecture designed for input/output ("I/O") intensive applications and are the industry's fastest CPLDs. These families provides performance of up to 200 MHz (3.5 nanosecond propagation delay), densities of 1,000 to 8,000 gates and are available in 44-to 208-pin standard surface mount packages. ispLSI 3000/E: The ispLSI 3000/E family incorporates an enhanced CPLD architecture to target higher density applications while retaining high performance. This family provides densities of 7,000 to 20,000 gates, performance of up to 125 MHz (7.5 nanosecond propagation delay), and is available in 160- to 432-pin surface mount packages. ispLSI 5000V: Introduced in fiscal 1999, the SuperWIDE-TM- 3.3-volt ispLSI 5000V family is based on an entirely new CPLD architecture that incorporates a 68-input logic block. This innovative logic block architecture, the industry's widest, makes the 5000V family an ideal solution for 32-bit and emerging 64-bit control logic applications. This family provides densities of 12,000 to 24,000 gates, performance of up to 125 MHz (7.5 nanoseconds propagation delay), and is available in 192- to 388-pin surface mount packages. ispLSI 8000: Introduced in fiscal 1999, the SuperBIG-TM- 5-volt ispLSI 8000 family utilizes an entirely new hierarchical CPLD architecture designed to efficiently implement large, register intensive, logic applications. This family provides densities of 25,000 to 50,000 gates, performance of up to 110 MHz (8.5 nanoseconds propagation delay), and is available in 272- to 492-pin surface mount packages. ispGAL-Registered Trademark-: This proprietary family combines in-system programmability with the industry standard 22V10 low-density architecture. Offered with performance of up to 200 MHz, (5.0 nanosecond propagation delay), the ispGAL family is available in both 5-volt and 3.3-volt operating supply versions. 4
ispGDX-TM-: This family extends in-system programmability to the circuit board level using an innovative digital cross-point switch architecture. Offered with propagation delays as low as 5.0 nanoseconds, up to 160 I/O and complete pin-to-pin signal routing, the ispGDX is targeted towards digital signal interconnect and interface applications. The Company plans to continue to introduce new families of ISP products, as well as improve the performance of existing product families based on market needs. SOFTWARE DEVELOPMENT TOOLS. All ISP products are supported by ispEXPERT-TM-, the Company's third generation software development tool suite. Supporting both the PC and UNIX platforms, ispEXPERT allows a customer to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign I/O pins and critical speed paths, debug and floorplan a design, execute automatic place and route tasks and download a program to an ISP device. Seamlessly integrated with third-party electronic design automation ("EDA") environments, ispEXPERT leverages customers' prior investments in products offered by Aldec, Cadence, Mentor Graphics, OrCAD, Synopsys, Synplicity, Viewlogic and Veribest. In the future, the Company plans to continue to enhance and expand its development tool offerings. The Company also provides a variety of software algorithms that support in-system programming of the Company's ISP devices via multiple formats and mechanisms. These software products include ispCODE-TM-, Turbo ispDOWNLOAD-TM-, ispREMOTE-TM-, ispATE-TM-, and ispSVF-TM-. NON-ISP PRODUCTS. The Company offers the industry's broadest line of low-density CMOS PLDs based on its 16 families of GAL products offered in over 180 speed, power, package and temperature range combinations. GAL devices range in complexity from approximately 200 to 1,000 logic gates and are typically assembled in 20-, 24- and 28-pin standard dual in-line packages and in 20- and 28-pin standard plastic leaded chip carrier packages. The Company offers the industry standard GAL16V8, GAL20V8, GAL22V10, GAL20RA10 and GAL20XV10 architectures in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. The Company also offers several proprietary extension architectures, the GAL26CV12, GAL18V10, GAL16VP8, GAL20VP8, GAL6001/2, GAL16V8Z and GAL20V8Z, each of which is optimized for specific applications. The Company also offers a full range of 3.3-volt industry standard architectures, the GAL16LV8, GAL20LV8, GAL22LV10 and GAL26CLV12 in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. The Company's non-ISP products are supported by industry standard software and hardware development tools marketed by independent manufacturers specifically for PLD applications. PRODUCT DEVELOPMENT The Company places substantial emphasis on new product development and believes that continued investment in this area is required to maintain its competitive position. See "Factors Affecting Future Results." The Company's product development activities emphasize new proprietary ISP products, enhancement of existing products and process technologies and improvement of software development tools. Product development activities occur in the Company's Hillsboro, Oregon headquarters, Milpitas, California product development center and Corsham, England and Shanghai, China design centers. 5
Research and development expenses were $27.8 million, $32.0 million and $33.2 million in fiscal years 1997, 1998 and 1999, respectively. The Company expects to continue to make significant investments in research and development in the future. OPERATIONS The Company does not manufacture its own silicon wafers and has historically maintained strategic relationships with large semiconductor manufacturers to source finished silicon wafers. This allows internal resources to be focused on product, process and market development. In addition, assembly is performed for the Company by outside suppliers. The Company performs certain test operations and reliability and quality assurance processes internally, as the Company believes it can add significant customer value in these areas. The Company has achieved ISO 9001 quality certification, an indication of the Company's high internal operational standards. WAFER FABRICATION The majority of the Company's silicon wafer requirements are currently supplied by Seiko Epson Corporation ("Seiko Epson") in Japan pursuant to an agreement with Epson Electronics America, Inc. ("EEA", formerly SMOS Systems, Inc. "S MOS"), an affiliated U.S. distributor of Seiko Epson. See "Licenses and Agreements - Seiko Epson/S MOS." The Company negotiates wafer volumes, prices and terms with Seiko Epson and EEA on a periodic basis. In addition, the Company receives silicon wafers from the United Microelectronics Corporation Group of affiliated companies ("UMC Group") in Taiwan pursuant to a series of agreements entered into in 1995. Wafer prices and other purchase terms related to this commitment are subject to periodic adjustment. See "Licenses and Agreements - UMC Group." A significant interruption or shortage in wafer supply from Seiko Epson through EEA or from the UMC Group would have a material adverse effect on the Company's business. A significant or unexpected deterioration in the silicon wafer quality or yield levels achieved by Seiko Epson or the UMC Group could also have a material adverse effect on the Company's business. See "Factors Affecting Future Results." ASSEMBLY After wafer fabrication and initial testing, the Company ships wafers to independent subcontractors for assembly. During assembly, wafers are separated into individual die and encapsulated in plastic or ceramic packages. Presently, the Company has qualified long-term assembly partners in Hong Kong, Malaysia, the Philippines, South Korea, Taiwan and the United States. See "Factors Affecting Future Results." TESTING The Company electrically tests the die on each wafer prior to shipment for assembly. Following assembly, prior to customer shipment, each product undergoes final testing using test equipment, techniques and quality assurance procedures. Final testing on certain products is performed at independent contractors in Malaysia, the Philippines, South Korea and the United States. MARKETING, SALES AND CUSTOMERS 6
The Company sells its products directly to end customers through a network of independent manufacturers' representatives and indirectly through a network of independent distributors. The Company also employs a direct sales management and field applications engineering organization to support its end customers and indirect sales resources. The Company's end customers are primarily original equipment manufacturers in the fields of communication, computing, industrial and military systems. At April 3, 1999, the Company utilized 21 manufacturers' representatives and four distributors in North America. Arrow Electronics, Inc., Avnet, Inc. and Marshall Industries provide full distribution coverage, while Future Electronics provides regional distribution coverage in Canada. The Company has also established export sales channels in over 30 foreign countries through a network of over 30 sales representatives and distributors. Approximately one-half of the Company's North American sales and most of its export sales are made through distributors. The Company protects each of its North American distributors and some of its foreign distributors against reductions in published prices, and expects to continue this policy in the foreseeable future. The Company also allows returns from these distributors of unsold products under certain conditions. For these reasons, the Company does not recognize revenue until products are resold by these distributors. The Company provides technical and marketing support to end customers with engineering staff based in the Company's headquarters, design centers and selected field sales offices. The Company maintains 21 domestic and international sales offices. These offices are located in the metropolitan areas of Atlanta, Boston, Chicago, Dallas, Los Angeles, Minneapolis, Orange County, Orlando, Portland, Raleigh, San Diego, San Jose, Hong Kong, London, Milan, Munich, Paris, Seoul, Shanghai, Taipei and Tokyo. Export sales accounted for 49%, 51% and 50% of the Company's total revenue in fiscal 1997, 1998 and 1999, respectively. Both export and domestic sales are denominated in U.S. dollars, with the exception of sales to Japan, which are dominated in yen. If export sales decline significantly there will be a material adverse impact on the Company's business. See "Factors Affecting Future Results." The Company's products are sold to a large and diverse group of customers. No individual customer or distributor accounted for more than 10% of total revenue in fiscal 1997, 1998 or 1999. No export sales to any individual country accounted for more than 10% of total revenue in fiscal 1997, 1998 or 1999. BACKLOG The Company's backlog of scheduled and released orders as of April 3, 1999 was approximately $30.4 million as compared to approximately $31.8 million as of March 28, 1998. The Company's backlog consists of direct OEM and distributor orders scheduled for delivery within the next 90 days. Distributor orders accounted for the majority of the backlog in both periods. Direct OEM customer orders may be changed, rescheduled or cancelled under certain circumstances without penalty prior to shipment. Additionally, distributor orders generally may be changed, rescheduled or cancelled without penalty prior to shipment. Furthermore, distributor shipments are subject to rights of return and price adjustment. Revenue associated with distributor shipments is not recognized until the product is resold to an end customer. In recent periods, the majority of the Company's revenue has resulted from orders placed and filled within the same period ("turns orders"). By definition, turns orders are not captured in a backlog measurement made at the beginning of a period. The Company does not anticipate a 7
significant change in this business pattern. For all these reasons, backlog as of any particular date should not be used as a predictor of revenue for any future period. COMPETITION The semiconductor industry is intensely competitive and characterized by rapid rates of technological change, product obsolescence and price erosion. The Company's current and potential competitors include a broad range of semiconductor companies from large, established companies to emerging companies, many of which have greater financial, technical, manufacturing, marketing and sales resources. The principal competitive factors in the PLD market include product features, price, customer support, and sales, marketing and distribution strength. The availability of competitive software development tools is also critical. In addition to product features such as density, speed, power consumption, reprogrammability, design flexibility and reliability, competition in the PLD market occurs on the basis of price and market acceptance of specific products and technology. The Company believes that it competes favorably with respect to each of these factors. The Company intends to continue to address these competitive factors by working to continually introduce product enhancements and new products, by seeking to establish its products as industry standards in their respective markets, and by working to reduce the manufacturing cost of its products over their respective life cycles. In the ISP PLD market, the Company primarily competes directly with Altera and Xilinx, both of which offer competing products. The Company also competes indirectly with other PLD suppliers as well as other semiconductor companies providing non-PLD based logic solutions. As the Company and these other companies seek to expand their markets, competition may increase. Although to date the Company has not experienced significant competition from companies located outside the United States, such companies may become a more significant competitive factor in the future. As the Company and its current competitors seek to expand their markets, competition may increase. Any such increases in competition could have a material adverse effect on the Company's operating results. See "Factors Affecting Future Results." PATENTS The Company seeks to protect its products and wafer fabrication process technologies primarily through patents, trade secrecy measures, copyrights, mask work protection, trademark registrations, licensing restrictions, confidentiality agreements and other approaches designed to protect proprietary information. There can be no assurance that others may not independently develop competitive technology not covered by the Company's intellectual property rights or that measures taken by the Company to protect its technology will be effective. See "Factors Affecting Future Results." The Company holds numerous domestic, European and Japanese patents on its PLD products and has patent applications pending in the United States, Japan and Europe. There can be no assurance that pending patent applications or other applications that may be filed will result in issued patents, or that any issued patents will survive challenges to their validity. Although the Company believes that its patents have value, there can be no assurance that the Company's patents, or any additional patents that may be issued in the future, will provide 8
meaningful protection from competition. The Company believes its success will depend primarily upon the technical expertise, experience, creativity and the sales and marketing abilities of its personnel. Patent and other proprietary rights infringement claims are common in the semiconductor industry. There can be no assurance that, with respect to claims made against the Company, the Company could obtain a license on terms or under conditions that would not have a material adverse effect on the Company. See "Factors Affecting Future Results." LICENSES AND AGREEMENTS SEIKO EPSON/EPSON ELECTRONICS AMERICA, INC. EEA, an affiliated U.S. distributor of Seiko Epson, has agreed to provide manufactured wafers to the Company in quantities based on six-month rolling forecasts provided by the Company. The Company has committed to buy certain minimum quantities of wafers per month. Wafers for the Company's products are manufactured in Japan at Seiko Epson's wafer fabrication facilities and are delivered to the Company by EEA. Prices for the wafers obtained from EEA are reviewed and adjusted periodically. In July 1994, the Company entered into an advance production payment agreement with Seiko Epson and EEA, under which it advanced to Seiko Epson $42 million during fiscal 1995 to be used by Seiko Epson to finance additional sub-micron semiconductor wafer manufacturing capacity. Under the terms of the agreement, the advance is to be repaid in the form of advanced technology sub-micron semiconductor wafers. In conjunction with the advance production payment agreement, the Company also paid $2 million during fiscal 1995 for the development of sub-micron process technology and the fabrication of engineering wafers. These agreements call for wafers to be supplied by Seiko Epson through EEA pursuant to a purchase agreement concluded with EEA. As of April 3, 1999, all wafers pursuant to these agreements had been received by the Company. In March 1997, the Company entered into a second advance production payment agreement with Seiko Epson and EEA under which it agreed to advance approximately $85 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility. The timing of the payments is related to certain milestones in the development of the facility. Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period. The agreement calls for wafers to be supplied by Seiko Epson through EEA pursuant to purchase agreements concluded with EEA. The Company also has an option under the agreement to advance Seiko Epson an additional $60 million for additional wafer supply under similar terms. The first payment under this agreement, approximately $17.0 million, was made during fiscal 1997. During fiscal 1998, the Company made two additional payments aggregating approximately $34.2 million. UMC GROUP The Company entered into a series of agreements with UMC in September 1995 pursuant to which the Company agreed to join UMC and several other companies to form a separate Taiwanese company, UICC, for the purpose of building and operating an advanced semiconductor manufacturing facility in Taiwan, Republic of China. Under the terms of the agreement, the Company invested approximately $49.7 million between fiscal 1996 and fiscal 1998 9
for an approximate 10% equity interest in UICC and the right to receive a percentage of the facility's wafer production at market prices. In October 1997, the UICC foundry was substantially destroyed by fire. UMC, the majority owner of UICC, has informed the Company that this loss has been substantially recovered by an insurance settlement and additional investment income. In June 1999, the Board of Directors of UICC and the Board of Directors of UMC voted in favor of merging UICC into UMC. The matter is scheduled for a UMC shareholder vote in July 1999. The Company has received assurance that its capacity rights would be preserved in the event of this merger. Accordingly, management of the Company believes that its investment in UICC is not impaired. FACTORS AFFECTING FUTURE RESULTS Notwithstanding the objectives, projections, estimates and other forward-looking statements in this Annual Report, the Company's future operating results will continue to be subject to quarterly variations based on a wide variety of risks. These risks include, but are not limited to: OUR WAFER SUPPLY COULD BE INTERRUPTED OR REDUCED AND RESULT IN A SHORTAGE OF FINISHED PRODUCTS AVAILABLE FOR SALE. We do not manufacture finished silicon wafers. Currently all our silicon wafers are manufactured by Seiko Epson in Japan and the UMC Group, a group of affiliated companies in Taiwan. If Seiko Epson, through its U.S. affiliate Epson Electronics America, or the UMC Group significantly interrupts or reduces our wafer supply, our operating results would be adversely affected. In the past, we have experienced delays in obtaining wafers and in securing supply commitments from our foundries. At present, we anticipate that our supply commitments are adequate. However, these existing supply commitments may not be sufficient for us to satisfy customer demand in future periods. Additionally, during times of capacity shortage, notwithstanding our supply commitments we may still have difficulty in obtaining wafer deliveries consistent with the supply commitments. We negotiate wafer prices and supply commitments on at least an annual basis. If Seiko Epson, Epson Electronics America or the UMC Group reduces our supply commitment or increases our wafer prices, and we cannot find alternative sources of wafer supply, our operating results could be adversely affected. Many other factors that could disrupt our wafer supply are beyond our control. Since worldwide manufacturing capacity for silicon wafers is limited and inelastic, we could be adversely affected by significant industry wide increases in overall wafer demand or interruptions in wafer supply. Additionally, a disruption of Seiko Epson's or the UMC Group's foundry operations as a result of a fire, earthquake or other natural disaster would disrupt our wafer supply and would have an adverse effect on our operating results. IF OUR FOUNDRY PARTNERS EXPERIENCE QUALITY OR YIELD PROBLEMS, WE MAY FACE A SHORTAGE OF FINISHED PRODUCTS AVAILABLE FOR SALE. We depend on our foundries to deliver reliable silicon wafers with acceptable yields in a timely manner. As is common in our industry, we have experienced wafer yield problems and delivery delays in the past. If our 10
foundries are unable to produce silicon wafers that meet our specifications, with acceptable yields, for a prolonged period, our operating results could be adversely affected. Substantially all of our revenues are derived from products based on a specialized silicon wafer manufacturing process technology called E2CMOS-Registered Trademark-. The reliable manufacture of high performance E2CMOS semiconductor wafers is a complicated and technically demanding process requiring: - - a high degree of technical skill; - - state-of-the-art equipment; - - the absence of defects in the masks used to print circuits on a wafer; - - the elimination of minute impurities and errors in each step of the fabrication process; and - - effective cooperation between the wafer supplier and the circuit designer. As a result, our foundries may experience difficulties in achieving acceptable quality and yield levels when manufacturing our silicon wafers. OUR PRODUCTS MAY NOT BE COMPETITIVE IF WE ARE UNSUCCESSFUL IN MIGRATING OUR MANUFACTURING PROCESSES TO MORE ADVANCED TECHNOLOGIES. In order to develop new products and maintain the competitiveness of existing products, we need to migrate to more advanced wafer manufacturing processes that utilize larger wafer sizes and smaller device geometries. We may also utilize additional foundries. Since we depend upon foundries to provide their facilities and support for our process technology development, we may experience delays in the availability of advanced wafer manufacturing process technologies at existing or new wafer fabrication facilities. As a result, volume production of our advanced E2CMOS-Registered Trademark- process technologies at the new fabs of Seiko Epson, the UMC Group or future foundries may not be achieved. This could have an adverse effect on our operating results. WE MAY BE UNSUCCESSFUL IN DEFINING AND DEVELOPING NEW PRODUCTS REQUIRED TO MAINTAIN OR GROW OUR BUSINESS. As a semiconductor company, we operate in a dynamic environment marked by rapid product obsolescence. Our future success depends on our ability to introduce new or improved products that meet customer needs while achieving acceptable margins. If we fail to introduce these new products in a timely manner or these products fail to achieve market acceptance, our business and financial condition will be adversely affected. The introduction of new products in a dynamic market environment presents significant business challenges. Product development commitments and expenditures must be made well in advance of product sales. The success of a new product depends on accurate forecasts of long-term market demand and future technology developments. Our future revenue growth is dependent on market acceptance of our new proprietary ISP-TM- product families and the continued market acceptance of our proprietary software development tools. The success of these products is dependent on a variety of specific technical factors including: - - successful product definition; - - timely and efficient completion of product design; 11
- - timely and efficient implementation of wafer manufacturing and assembly processes; - - product performance; and - - the quality and reliability of the product. If, due to these or other factors, our new ISP products do not achieve market acceptance, our business and financial condition will be adversely affected. WE MAY EXPERIENCE UNEXPECTED DIFFICULTIES INTEGRATING VANTIS CORPORATION. Integration of Vantis has begun. If integration is unsuccessful, or more difficult, or more time consuming than originally planned, we may incur unexpected disruptions to our ongoing business. These disruptions may have an adverse effect on our operations and financial results. Further, the following specific factors may adversely affect our ability to smoothly and quickly integrate the business of Vantis: - - We may experience unexpected losses of key employees or customers; - - We may experience difficulties and delays in conforming the standards, processes, procedures and controls of our two businesses; - - We may experience unexpected costs and discover unexpected liabilities; - - We may not receive product manufacturing and administrative services from Vantis former parent corporation, AMD at a level of quality and timeliness consistent with the historical delivery of this support; - - We may not achieve expected levels of revenue growth, cost reduction and profitability improvement; and - - We may not be able to coordinate our new product and process development in a way which permits us to bring new technologies to the market in a timely manner. CONTINUED DETERIORATION OF CONDITIONS IN ASIA MAY DISRUPT OUR EXISTING SUPPLY ARRANGEMENTS AND RESULT IN A SHORTAGE OF FINISHED PRODUCTS AVAILABLE FOR SALE. Our two silicon wafer suppliers operate fabs located in Asia. Our finished silicon wafers are assembled and tested by independent subcontractors located in Hong Kong, Malaysia, the Philippines, South Korea and Taiwan. A prolonged interruption in our supply from any of these subcontractors could have an adverse effect on our operating results. Although we have yet not experienced significant supply interruptions, the economic, financial, social and political situation in Asia has recently been volatile. Financial difficulties, governmental actions or restrictions, prolonged work stoppages or any other difficulties experienced by these suppliers may disrupt our supply and could have an adverse effect on our operating results. Our wafer purchases from Seiko Epson are denominated in Japanese yen. The value of the dollar with respect to the yen has fluctuated in the past and may not remain stable in the future. Future substantial deterioration of dollar-yen exchange rates could have an adverse effect on our operating results. EXPORT SALES ACCOUNT FOR A SUBSTANTIAL PORTION OF OUR REVENUES AND MAY DECLINE IN THE FUTURE DUE TO ECONOMIC AND GOVERNMENTAL UNCERTAINTIES. Our export sales are affected by unique risks frequently associated with foreign economies including: - - changes in local economic conditions; 12
- - exchange rate volatility; - - governmental controls and trade restrictions; - - export license requirements and restrictions on the export of technology; - - political instability; - - changes in tax rates, tariffs or freight rates; - - interruptions in air transportation; and - - difficulties in staffing and managing foreign sales offices. For example, our export sales have recently been affected by the Asian economic crisis. Significant changes in the economic climate in the foreign countries where we derive our export sales could have an adverse effect on our operating results. IF OUR ASSEMBLY AND TEST SUBCONTRACTORS EXPERIENCE QUALITY OR YIELD PROBLEMS, WE MAY FACE A SHORTAGE OF FINISHED PRODUCTS AVAILABLE FOR SALE. We rely on subcontractors to assemble and test our devices with acceptable quality and yield levels. As is common in our industry, we have experienced quality and yield problems in the past. If we experience prolonged quality or yield problems in the future, there could be an adverse affect on our operating results. The majority of our revenue is derived from semiconductor devices assembled in advanced packages. The assembly of advanced packages is a complex process requiring: - - a high degree of technical skill; - - state-of-the-art equipment; - - the absence of defects in lead frames used to attach semiconductor devices to the package; - - the elimination of raw material impurities and errors in each step of the process; and - - effective cooperation between the assembly subcontractor and the device manufacturer. As a result, our subcontractors may experience difficulties in achieving acceptable quality and yield levels when assembling and testing our semiconductor devices. THE CYCLICAL NATURE OF THE SEMICONDUCTOR INDUSTRY MAY LIMIT OUR ABILITY TO MAINTAIN OR GROW REVENUE AND PROFIT LEVELS DURING FUTURE INDUSTRY DOWNTURNS. The semiconductor industry is highly cyclical, to a greater extent than other less dynamic or less technology-driven industries. In the past, our financial performance has been negatively affected by significant downturns in the semiconductor industry as a result of: - - the cyclical nature of the demand for the products of semiconductor customers; - - general reductions in inventory levels by customers; - - excess production capacity; and - - accelerated declines in average selling prices. If these or other conditions in the semiconductor industry occur in the future, there could be an adverse effect on our operating results. 13
OUR STOCK PRICE MAY CONTINUE TO EXPERIENCE LARGE SHORT-TERM FLUCTUATIONS WHICH MAY RESULT IN INVESTORS LOSING ALL OR PART OF THEIR INVESTMENT. In recent years, the price of our common stock has fluctuated greatly. These price fluctuations have been rapid and severe and have left investors little time to react. The price of our common stock may continue to fluctuate greatly in the future due to a variety of company specific factors, including: - - quarter to quarter variations in our operating results; - - shortfalls in revenues or earnings from levels expected by securities analysts; - - announcements of technological innovations or new products by other companies. WE MAY NOT BE ABLE TO SUCCESSFULLY COMPETE IN THE HIGHLY COMPETITIVE SEMICONDUCTOR INDUSTRY. The semiconductor industry is intensely competitive and many of our direct and indirect competitors have substantially greater financial, technological, manufacturing, marketing and sales resources. If we are unable to compete successfully in this environment, our future results will be adversely affected. The current level of competition in the programmable logic market is high and may increase as our market expands. We currently compete directly with companies that have licensed our products and technology or have developed similar products. We also compete indirectly with numerous semiconductor companies that offer products and solutions based on alternative technologies. These direct and indirect competitors are established multinational semiconductor companies as well as emerging companies. We also may experience significant competition from foreign companies in the future. WE MAY FAIL TO RETAIN OR ATTRACT THE SPECIALIZED TECHNICAL AND MANAGEMENT PERSONNEL REQUIRED TO SUCCESSFULLY OPERATE OUR BUSINESS. To a greater degree than most non-technology companies or larger technology companies, our future success depends on our ability to attract and retain highly qualified technical and management personnel. As a mid-sized company, we are particularly dependent on a relatively small group of key employees. Competition for skilled technical and management employees is intense within our industry. As a result, we may not be able to retain our existing key technical and management personnel. In addition, we may not be able to attract additional qualified employees in the future. If we are unable to retain existing key employees or are unable to hire new qualified employees, our operating results could be adversely affected. IF WE ARE NOT ABLE TO ADEQUATELY PROTECT OUR INTELLECTUAL PROPERTY RIGHTS OUR FINANCIAL RESULTS AND COMPETITIVE POSITION MAY SUFFER. Our success depends in part on our proprietary technology. However, we may fail to adequately protect this technology. As a result, we may lose our competitive position or face significant expense to protect or enforce our intellectual property rights. We intend to continue to protect our proprietary technology through patents, copyrights and trade secrets. Despite this intention, we may not be successful in achieving adequate protection. Claims allowed on any of our patents may not be sufficiently broad to protect our technology. Patents issued to us also may be challenged, invalidated or circumvented. Finally, our competitors may develop similar technology independently. 14
Companies in the semiconductor industry vigorously pursue their intellectual property rights. If we become involved in protracted intellectual property disputes or litigation we may utilize substantial financial and management resources, which could have an adverse effect on our operating results. We may also be subject to future intellectual property claims or judgements. If these were to occur, we may not be able to obtain a license on favorable terms or without our operating results being adversely affected. YEAR 2000 COMPLIANCE The Company is currently working to address the potential impact of the Year 2000 on the processing of information by the Company's computerized systems, including interfaces to its business partners. In June 1999, the Company completed its planned Year 2000 compliance activities with respect to its products and internal systems, software, equipment and facilities. Based solely on these activities, management believes that all products and material internal systems, software, equipment and facilities are currently Year 2000 compliant. The Company does not anticipate that potential Year 2000 issues will have a material adverse impact on the Company's financial position or operating results. In aggregate, approximately $2 million in expenses were incurred to fund Year 2000 compliance activities. However, the Company could be adversely impacted if any of our critical business partners were to experience a severe business interruption due to a failure to address their internal Year 2000 issues in a timely manner. The most reasonably likely worst case Year 2000 scenario is a temporary disruption in supplier deliveries or customer shipments. If a severe disruption occurs in either of these two areas and is not corrected in a timely manner, a revenue or profit shortfall may result in the first half of calendar year 2000. Based solely on responses received to date from our business partners, the Company has no reason to believe that there will be such a material adverse impact. However, if the responses received from our business partners are inaccurate or happen to change, then there could be such a material adverse impact. Management plans to evaluate Year 2000 business interruption scenarios and develop appropriate contingency plans by September 1999. EMPLOYEES As of April 3, 1999 the Company had 546 full-time employees. The Company believes that its future success will depend, in part, on its ability to continue to attract and retain highly skilled technical and management personnel. None of the Company's employees is subject to a collective bargaining agreement. The Company has never experienced a work stoppage and considers its employee relations good. ITEM 2. PROPERTIES. The Company's corporate headquarters are located in three adjacent buildings owned by the Company in Hillsboro, Oregon comprising a total of approximately 200,000 square feet. The Company leases, through 2001, a 41,000 square foot product development facility in Milpitas, California. The Company owns a 13,000 square foot research and development facility and approximately 6,000 square feet of dormitory facilities in Shanghai, China. The Company recently opened a third design center in Corsham, England in a facility leased on a short-term basis. The Company leases, on a short-term basis, office facilities for its domestic and international sales offices. Vantis leases corporate headquarter facilities in Sunnyvale, California, as well as research and development facilities in Texas and Colorado, and sales offices worldwide. 15
ITEM 3. LEGAL PROCEEDINGS. ADVANCED MICRO DEVICES, INC. V. ALTERA CORPORATION (CASE NO. C-94-20567-RMW, N. D. CAL.). This litigation, which began in 1994, involves multiple claims and counterclaims for patent infringement relating to Vantis Corporation's (formerly a wholly owned subsidiary of Advanced Micro Devices, Inc. ("AMD")) and Altera Corporation's programmable logic devices. The Company assumed this litigation in its acquisition from AMD of Vantis Corporation. In April 1999, the Federal Court of Appeal reversed the earlier jury and Court decisions and held that Altera is not licensed to the eight AMD patents-in-suit. Also in April 1999, and following the decision of the Federal Court of appeal, Altera filed a petition for rehearing. In June 1999, the Federal Court of Appeal denied Altera's petition for rehearing. In connection with its acquisition of Vantis Corporation, Lattice has agreed to assume both the claims against Altera and the claims by Altera against AMD. Although there can be no assurance as to the results of such litigation, based upon information presently known to management, we do not believe that the ultimate resolution of this lawsuit will have a material adverse effect on our business. The foregoing statement constitutes a forward-looking statement and the actual results may differ materially depending on a number of factors, including new court decisions and additional counterclaims made by other parties to such litigation. ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS. Not applicable. 16
ITEM 4(a). EXECUTIVE OFFICERS OF THE REGISTRANT. As of June 14, 1999, the executive officers of the Company are as set forth below. <TABLE> <CAPTION> Name Age Position - ------------------ --- ------------------------------------------------ <S> <C> <C> Cyrus Y. Tsui 53 President, Chief Executive Officer and Chairman of the Board Steven A. Laub 40 Senior Vice President and Chief Operating Officer Stephen A. Skaggs 36 Senior Vice President, Chief Financial Officer and Secretary Stephen M. Donovan 48 Corporate Vice President, Sales Jonathan K. Yu 58 Corporate Vice President, Business Development Martin R. Baker 43 Vice President and General Counsel Randy D. Baker 40 Vice President, Manufacturing Albert L. Chan 49 Vice President and General Manager, Lattice Silicon Valley Thomas J. Kingzett 52 Vice President, Reliability and Quality Assurance Stanley J. Kopec 48 Vice President, Corporate Marketing Rodney F. Sloss 55 Vice President, Finance Kenneth K. Yu 51 Vice President and Managing Director, Lattice Asia </TABLE> Executive officers of the Company are appointed by the Board of Directors to serve at the discretion of the Board and hold office until the officers' successors are appointed. Cyrus Y. Tsui joined the Company in September 1988 as President, Chief Executive Officer and Director, and in March 1991 was named Chairman of the Board. From 1987 until he joined the Company, Mr. Tsui was Corporate Vice President and General Manager of the Programmable Logic Division of AMD. He was Vice President and General Manager of the Commercial Products Division of Monolithic Memories Incorporated from 1983 until the merger with AMD in 1987. Mr. Tsui has held technical and managerial positions in the 17
semiconductor industry for over 30 years. He has worked in the programmable logic industry since its inception. Steven A. Laub joined the Company in June 1990 as Vice President and General Manager. He was elected Senior Vice President and Chief Operating Officer in August 1996. Stephen A. Skaggs joined the Company in December 1992 as Director, Corporate Development. He was elected Senior Vice President, Chief Financial Officer and Secretary in August 1996. Stephen M. Donovan joined the Company in October 1989 and has served as Director of Marketing and Director of International Sales. He was elected Vice President, International Sales in August 1993. He was elected Corporate Vice President, Sales, in May 1998. Mr. Donovan has worked in the programmable logic industry since 1982. Jonathan K. Yu joined the Company in February 1992 as Vice President, Operations. He was elected Corporate Vice President, Business Development in August 1996. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 30 years. Martin R. Baker joined the Company in January 1997 as Vice President and General Counsel. From 1991 until he joined the Company, Mr. Baker held legal positions with Altera Corporation. Randy D. Baker joined the Company in April 1985 as Manager, Manufacturing and was promoted in 1988 to Director, Manufacturing. He was elected Vice President, Manufacturing in August 1996. Mr. Baker has worked in the semiconductor industry for over 15 years. Albert L. Chan joined the Company in May 1989 as California Design Center Manager and was promoted in 1991 to Director, California Product Development Center. He was elected Vice President, California Product Development in August 1993. He was elected Vice President and General Manager, Lattice Silicon Valley, in August 1997. Mr. Chan has worked in the programmable logic industry since 1983. Thomas J. Kingzett joined the Company in July 1992 as Director, Reliability and Quality Assurance. He was elected Vice President, Reliability and Quality Assurance in May 1998. Mr. Kingzett has worked in the semiconductor industry for over 25 years. Stanley J. Kopec joined the Company in August 1992 as Director, Marketing. He was elected Vice President, Corporate Marketing in May 1998. Mr. Kopec has worked in the programmable logic industry since 1985. Rodney F. Sloss joined the Company in May 1994 as Vice President, Finance. Prior to joining the Company, Mr. Sloss served as Chief Financial Officer of The Alexander Haagen Company, a real estate developer. Kenneth K. Yu joined the Company in January 1991 as Director of Process Technology. He has served as Managing Director, Lattice Asia since November 1992 and was elected Vice President, Lattice Asia in August 1993. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 25 years. 18
PART II ITEM 5. MARKET FOR THE REGISTRANT'S COMMON STOCK AND RELATED STOCKHOLDER MATTERS. The Company's common stock is traded on the over-the-counter market and prices are quoted on the Nasdaq National Market under the symbol "LSCC". The following table sets forth the high and low sale prices for the common stock for the last two fiscal years and for the period since April 3, 1999. On June 17, 1999, the last reported sale price of the common stock was $57 3/4. As of June 17, 1999, the Company had approximately 311 stockholders of record. <TABLE> <CAPTION> High Low ---- --- <S> <C> <C> Fiscal 1998: First Quarter. . . . . . . . . . . . . . . $62 5/8 $41 1/2 Second Quarter . . . . . . . . . . . . . . 74 1/2 54 7/8 Third Quarter. . . . . . . . . . . . . . . 67 1/2 45 Fourth Quarter . . . . . . . . . . . . . . 57 39 3/4 Fiscal 1999: First Quarter. . . . . . . . . . . . . . . $54 5/8 $25 5/8 Second Quarter . . . . . . . . . . . . . . 36 5/8 23 1/4 Third Quarter. . . . . . . . . . . . . . . 46 1/2 18 7/8 Fourth Quarter . . . . . . . . . . . . . . 56 5/16 37 3/4 Fiscal 2000: First Quarter (through June 28, 1999). . . $61 7/8 $38 1/16 </TABLE> The payment of dividends on the common stock is within the discretion of the Company's Board of Directors. The Company intends to retain earnings to finance the growth of its business. The Company has not paid cash dividends on its common stock and the Board of Directors does not expect to declare cash dividends on the common stock in the near future. ITEM 6. SELECTED FINANCIAL DATA. The information required by this Item is set forth in the Company's 1999 Annual Report to Stockholders at page 15 under the caption "Selected Financial Data", which information is incorporated herein by reference. 19
ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS. The information required by this Item is set forth in the Company's 1999 Annual Report to Stockholders at pages 10 through 14 under the caption "Management's Discussion and Analysis of Financial Condition and Results of Operations", which information is incorporated herein by reference. Item 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURES ABOUT MARKET RISK. As of April 3, 1999 and March 28, 1998, the Company's investment portfolio consisted of fixed income securities of $293.4 million and $245.5 million respectively. As with all fixed income instruments, these securities are subject to interest rate risk and will decline in value if market interest rates increase. If market rates were to increase immediately and uniformly by 10% from levels as of April 3, 1999 and March 28, 1998, the decline in the fair value of the portfolio would not be material. Further, the Company has the ability to hold its fixed income investments until maturity and, therefore, the Company would not expect to recognize such an adverse impact in income or cash flows. The Company has international subsidiary and branch operations. Additionally, the majority of the Company's silicon wafer purchases are denominated in Japanese yen. The Company is therefore subject to foreign currency rate exposure. To mitigate rate exposure with respect to yen-denominated wafer purchases, the Company maintains yen-denominated bank accounts and bills it Japanese customers in yen. The yen bank deposits are utilized to hedge yen-denominated wafer purchases against specific and firm wafer purchases. If the foreign currency rates fluctuate by 10% from rates at April 3, 1999 and March 28, 1998, the effect on the company's consolidated financial statements would not be material. However, there can be no assurance that there will not be a material impact in the future. ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA. FINANCIAL STATEMENTS The information required by this Item is set forth in the Company's 1999 Annual Report to Stockholders, at pages 16 through 27, which information is incorporated herein by reference. <TABLE> <CAPTION> Page ---- <S> <C> FINANCIAL STATEMENT SCHEDULES Report of Independent Accountants on Financial Statement Schedule. . . . S-1 Schedule VIII - Valuation and qualifying accounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-2 </TABLE> No other schedules are included because the required information is inapplicable, not required or is presented in the financial statements or related notes thereto. 20
ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE. Not applicable. With the exception of the information expressly incorporated by reference from the Annual Report to Stockholders into Parts II and IV of this Form 10-K, the Company's Annual Report to Stockholders is not to be deemed filed as part of this Report. 21
PART III Certain information required by Part III is omitted from this Report in that the Company will file its definitive proxy statement for the Annual Meeting of Stockholders to be held on August 9, 1999, pursuant to Regulation 14A of the Securities Exchange Act of 1934 (the "Proxy Statement"), not later than 120 days after the end of the fiscal year covered by this Report, and certain information included in the Proxy Statement is incorporated herein by reference. With the exception of the information expressly incorporated by reference from the Proxy Statement, the Company's Proxy Statement is not to be deemed filed as a part of this report. ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT. The information required by this Item with respect to directors of the Company is included under "Proposal 1: Election of Directors" in the Company's Proxy Statement, which information is incorporated herein by reference. Information with respect to executive officers of the Company is included under Item 4(a) of Part I of this Report and is incorporated herein by reference. ITEM 11. EXECUTIVE COMPENSATION. The information required by this Item with respect to executive compensation is included under "Proposal 1: Election of Directors-Directors," "Executive Compensation" and "Comparison of Total Cumulative Stockholder Return" in the Company's Proxy Statement, which information is incorporated herein by reference. ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT. The information required by this Item is included in the Company's Proxy Statement under the caption "Security Ownership of Certain Beneficial Owners and Management", which information is incorporated herein by reference. ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS. The information required by this Item is included under "Proposal 1: Election of Directors - Transactions with Management" in the Company's Proxy Statement, which information is incorporated herein by reference. 22
PART IV ITEM 14. EXHIBITS, FINANCIAL STATEMENT SCHEDULES AND REPORTS ON FORM 8-K. <TABLE> <S> <C> (a)(1) and (2) FINANCIAL STATEMENTS AND FINANCIAL STATEMENT SCHEDULES. The information required by this Item is included under Item 8 of this Report. (a)(3) EXHIBITS. 3.1 The Company's Certificate of Incorporation, as amended (including (i) the Company's Certificate Eliminating Matters set forth in Certificates of Designation with respect to Series A, Series B, Series D and Series E, dated February 15, 1990; (ii) the Company's Restated Certificate of Incorporation, as amended, incorporated by reference to Exhibit 3.1 filed with the Company's Annual Report on Form 10-K for the fiscal year ended March 31, 1990; (iii) the Company's Certificate of Designation of Rights, Preferences and Privileges of Series A participating Preferred Stock incorporated by reference to Exhibit 1 filed with the Company's Registration Statement on Form 8-A on September 13, 1991; and (iv) the Certificate of Amendment, dated September 8, 1993, of the Company's Certificate of Incorporation, filed as an exhibit hereto). 3.2 The Company's Bylaws, as amended (including (i) the Company's Amended Bylaws, incorporated by reference to Exhibit 3.2 filed with the Company's Annual Report on Form 10-K for the fiscal year ended March 30, 1991; (ii) Amendment to the Company's Bylaws authorized by the Board of Directors on May 24, 1991, filed as an exhibit hereto; (iii) Amendment to the Company's Bylaws authorized by the Board of Directors on May 16, 1995, filed as an exhibit hereto; and (iv) Amendment to the Company's Bylaws authorized by the Board of Directors on February 4, 1997, filed as an exhibit hereto). 4.1 Preferred Shares Rights Agreement dated as of September 11, 1991 between Lattice Semiconductor Corporation and First Interstate Bank of Oregon, N.A., as Rights Agent (Incorporated by reference to Exhibit 1 filed with the Company's Registration Statement on Form 8-A on September 13, 1991). 10.3 Patent License Agreement dated November 10, 1989 between Monolithic Memories, Inc. and Lattice Semiconductor Corporation, as amended (Incorporated by reference to Exhibit 10.3, File No. 33-31231).(1) 10.7 Form of Distributor Agreement (Incorporated by reference to Exhibit 10.6, File No. 33-31231). 23
10.9 * Lattice Semiconductor Corporation 1988 Stock Incentive Plan, as amended (Incorporated by reference to Exhibit 10.9 filed with the Company's Annual Report on Form 10-K for the fiscal year ended March 28, 1992). 10.10 * Form of Stock Option Agreement (Incorporated by reference to Exhibit 10.9, File No. 33-31231). 10.11 * Employment Letter dated September 2, 1988 from Lattice Semiconductor Corporation to Cyrus Y. Tsui (Incorporated by reference to Exhibit 10.10, File No. 33-31231). 10.12 Form of Proprietary Rights Agreement (Incorporated by reference Exhibit 10.11, File No. 33-31231). 10.13 * Outside Directors Compensation Plan (Incorporated by reference to Exhibit 10.12, File No. 33-31231). 10.14 * Amended Outside Directors Stock Option Plan (Incorporated by reference to Exhibit 10.13, File No. 33-35427). 10.15 * 1993 Outside Directors Stock Option Plan (Incorporated by reference to Exhibit 10.15 filed with the Company's Annual Report on Form 10-K for the fiscal year ended April 3, 1993). 10.16 * Employee Stock Purchase Plan, as amended (Incorporated by reference to Exhibit 10.16 filed with the Company's Annual Report on Form 10-K for the fiscal year ended April 3, 1993). 10.17 Advance Production Payment Agreement dated July 5, 1994 among Lattice Semiconductor Corporation and Seiko Epson Corporation and S MOS Systems, Inc. (Incorporated by reference to Exhibit 10.17 filed with the Company's Annual Report on Form 10-K for the fiscal year ended April 1, 1995).(1) 10.18 Engineering Payment Agreement dated July 5, 1994 among Lattice Semiconductor Corporation and Seiko Epson Corporation and S MOS Systems, Inc. (Incorporated by reference to Exhibit 10.18 filed with the Company's Annual Report on Form 10-K for the fiscal year ended April 1, 1995. 10.19 Bridge Capacity Letter dated September 12, 1995 between Lattice Semiconductor Corporation and United Microelectronics Corporation. (Incorporated by reference to Exhibit 10.1 filed with the Company's Current Report on Form 8-K dated September 28, 1995)(1). 10.20 Foundry Venture Side Letter dated September 13, 1995 among Lattice Semiconductor Corporation, United Microelectronics Corporation and FabVen (Incorporated by reference 24
to Exhibit 10.2 filed with the Company's Current Report on Form 8-K dated September 28, 1995)(1). 10.21 FabVen Foundry Capacity Agreement dated as of August ___, 1995 among FabVen, United Microelectronics Corporation and Lattice Semiconductor Corporation (Incorporated by reference to Exhibit 10.3 filed with the Company's Current Report on Form 8-K dated September 28, 1995)(1). 10.22 Foundry Venture Agreement dated as of August ___, 1995, between Lattice Semiconductor Corporation and United Microelectronics Corporation (Incorporated by reference to Exhibit 10.4 filed with the Company's Current Report on Form 8-K dated September 28, 1995)(1). 10.23 Advance Production Payment Agreement dated March 17, 1997 among Lattice Semiconductor Corporation and Seiko Epson Corporation and S MOS Systems, Inc. (Incorporated by reference to Exhibit 10.23 filed with the Company's Annual Report on Form 10-K for the fiscal year ended March 29, 1997)(1). 10.24 * Lattice Semiconductor Corporation 1996 Stock Incentive Plan (Incorporated by reference to Exhibit 4.1 filed on Form S-8 dated November 7, 1996). 10.25 Form of North America Sales Representative Agreement. (Incorporated by reference to Exhibit 10.25 filed with the Company's Annual Report on Form 10-K for the fiscal year ended March 28, 1998). 10.26 Stock Purchase Agreement dated as of April 21, 1999 by and between Lattice Semiconductor Corporation and Advanced Micro Devices, Inc. (Incorporated by reference to Exhibit 2.1 filed with the Company's Current Report on Form 8-K dated April 21, 1999). 10.27 First Amendment to Stock Purchase Agreement dated as of June 7, 1999 entered into by and between Lattice Semiconductor Corporation and Advanced Micro Devices, Inc. 10.28 Second Amendment to Stock Purchase Agreement dated as of June 15, 1999 entered into by and between Lattice Semiconductor Corporation and Advanced Micro Devices, Inc. 10.29 Form 8-K for Lattice Semiconductor Corporation regarding June 15, 1999 acquisition of Vantis Corporation (Incorporated by reference to Company's Current Report on Form 8-K dated June 15, 1999 and filed June 25, 1999). 11.1 Computation of Net Income Per Share(2). 13.1 1999 Annual Report to Stockholders. 21.1 Subsidiaries of the Registrant. 23.1 Consent of Independent Accountants. 24.1 Power of Attorney (see pages 27-28). 27.1 Financial Data Schedule for Year Ended April 3, 1999. </TABLE> 25
______________ (1) Pursuant to Rule 24b-2 under the Securities Exchange Act of 1934, confidential treatment has been granted to portions of this exhibit, which portions have been deleted and filed separately with the Securities and Exchange Commission. (2) Incorporated by reference to Note 1 to the Consolidated Financial Statements in the Company's Annual Report to Stockholders for the fiscal year ended April 3, 1999. * Management contract or compensatory plan or arrangement required to be filed as an Exhibit to this Annual Report on Form 10-K pursuant to Item 14(c) thereof. (b) No reports on Form 8-K were filed during the last quarter of fiscal 1999. (c) See (a)(3) above. (d) See (a)(1) and (2) above. 26
SIGNATURES Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, the Registrant has duly caused this Report to be signed on its behalf by the undersigned, thereunto duly authorized, in the City of Hillsboro, State of Oregon, on the 1st of July, 1999. LATTICE SEMICONDUCTOR CORPORATION By: /s/Stephen A. Skaggs ----------------------------------------- Stephen A. Skaggs, Senior Vice President, Chief Financial Officer and Secretary POWER OF ATTORNEY KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears below constitutes and appoints Cyrus Y. Tsui and Stephen A. Skaggs, jointly and severally, his attorneys-in-fact, each with the power of substitution, for him in any and all capacities, to sign any amendments to this Report on Form 10-K, and to file the same, with exhibits thereto and other documents in connection therewith, with the Securities and Exchange Commission, hereby ratifying and confirming all that each of said attorneys-in-fact, or his substitute or substitutes, may do or cause to be done by virtue hereof. Pursuant to the requirements of the Securities Exchange Act of 1934, this Report has been signed below by the following persons on the 1st day of July, 1999 on behalf of the Registrant and in the capacities indicated: Signature Title - ------------------------- -------------------------------------------- /s/Cyrus Y. Tsui President, Chief Executive Officer - ------------------------- and Chairman of the Board (Principal Cyrus Y. Tsui Executive Officer) /s/Stephen A. Skaggs Senior Vice President, Chief Financial - ------------------------- Officer and Secretary (Principal Financial Stephen A. Skaggs Officer) /s/Mark O. Hatfield Director - ------------------------- Mark O. Hatfield /s/Daniel S. Hauer Director - ------------------------- Daniel S. Hauer 27
Signature Title - ------------------------- -------------------------------------------- /s/Harry A. Merlo Director - ------------------------- Harry A. Merlo /s/Larry W. Sonsini Director - ------------------------- Larry W. Sonsini /s/Douglas C. Strain Director - ------------------------- Douglas C. Strain 28
REPORT OF INDEPENDENT ACCOUNTANTS ON FINANCIAL STATEMENT SCHEDULE To the Board of Directors of Lattice Semiconductor Corporation Our audits of the consolidated financial statements referred to in our report dated April 21, 1999, except as to Note 13, which is as of June 15, 1999 appearing in the Annual Report to Stockholders of Lattice Semiconductor Corporation (which report and consolidated financial statements are incorporated by reference in this Annual Report on Form 10-K) also included an audit of the financial statement schedule listed in Item 14(a)(2) of this Form 10-K. In our opinion, this financial statement schedule presents fairly, in all material respects, the information set forth therein when read in conjunction with the related consolidated financial statements. PricewaterhouseCoopers LLP Portland, Oregon April 21, 1999 S-1
SCHEDULE VIII LATTICE SEMICONDUCTOR CORPORATION VALUATION AND QUALIFYING ACCOUNTS (IN THOUSANDS) <TABLE> <CAPTION> COLUMN A COLUMN B COLUMN C COLUMN D COLUMN E COLUMN F ---------- --------------------------------------------------------------- CHARGED TO BALANCE AT CHARGED TO OTHER WRITE-OFFS BALANCE BEGINNING OF COSTS AND ACCOUNTS NET OF AT END OF CLASSIFICATION PERIOD EXPENSES (DESCRIBE) RECOVERIES PERIOD -------------- ------------ --------- ----------- ---------- ---------- <S> <C> <C> <C> <C> <C> Year ended March 29, 1997: Allowance for deferred tax asset......... $2,336 $(340) -- -- $1,996 Allowance for doubtful accounts.......... 800 70 -- 4 874 ------ ------ ---- ------ ------ $3,136 $ (270) $ -- $ 4 $2,870 ------ ------ ---- ------ ------ ------ ------ ---- ------ ------ Year ended March 28, 1998: Allowance for deferred tax asset......... $1,996 $ (205) -- -- $1,791 Allowance for doubtful accounts.......... 874 3 -- (80) 797 ------ ------ ---- ------ ------ $2,870 $ (202) $ -- $ (80) $2,588 ------ ------ ---- ------ ------ ------ ------ ---- ------ ------ Year ended April 3, 1999: Allowance for deferred tax asset......... $1,791 $ (136) -- -- $1,655 Allowance for doubtful accounts.......... 797 70 -- 14 881 ------ ------ ---- ------ ------ $2,588 $ (66) $ -- $ 14 $2,536 ------ ------ ---- ------ ------ ------ ------ ---- ------ ------ </TABLE> S-2